1. Field of the Invention
The present invention relates to a semiconductor memory device to/from which stored data is input/output in synchronism with a clock signal.
2. Description of the Background Art
FIG. 18 is a schematic block diagram showing a synchronous semiconductor memory device to/from which signals are input/output in synchronism with a clock, and an information processing device for controlling the semiconductor memory device.
A semiconductor memory device 600 and an information processing device 601 are connected to each other by an input signal 609, a clock 610, and an output data signal 612. The semiconductor memory device 600 includes an input signal latching circuit 602 and a memory core 603, wherein the input signal latching circuit 602 and the memory core 603 are connected to each other by a latched signal 604. The memory core 603 includes a control circuit, a power supply circuit, a decoder circuit and a read circuit for operating the memory core 603.
The input signal latching circuit 602 latches the received input signal 609 in synchronism with the clock 610, and outputs the latched signal 604.
FIGS. 19A to 19C are timing diagrams each showing an input signal latching operation with a circuit configuration as shown in FIG. 18.
FIG. 19A is a timing diagram showing an input signal latching operation in a case where the input signal transitions before the rising edge of the clock.
FIG. 19B is a timing diagram showing an input signal latching operation in a case where the input signal timing is delayed with respect to that shown in FIG. 19A, whereby the input signal transitions after the rising edge of the clock, due to variations such as those in the voltage conditions of the device, those in the temperature conditions of the device, and those in the wire delay between the information processing device and the semiconductor memory device.
FIG. 19C is a timing diagram showing an input signal latching operation in a case where the input signal timing varies during the input signal latching operation due to variations such as those in the voltage conditions of the device, those in the temperature conditions of the device, and those in the wire delay between the information processing device and the semiconductor memory device.
In the illustrated examples, the input signal latching circuit 602 latches the input signal 609 at the rising edge of the input clock 610.
The input signal latching operation shown in the timing diagram of FIG. 19A will now be described.
As the input signal goes “H” (high level) at time T01a, the input signal being “H” is latched by the input signal latching circuit 602 at the following rising edge of the clock, thus bringing the latched signal to “H”.
As the input signal goes “L” (low level) at time T02a, the input signal being “L” is latched by the input signal latching circuit 602 at the following rising edge of the clock, thus bringing the latched signal to “L”.
As the input signal goes “H” at time T03a, the input signal being “H” is latched by the input signal latching circuit 602 at the following rising edge of the clock, thus bringing the latched signal to “H”.
As the input signal goes “L” at time T04a, the input signal being “L” is latched by the input signal latching circuit 602 at the following rising edge of the clock, thus bringing the latched signal to “L”.
With the timing shown in FIG. 19A, the latched signal has the same waveform as the input signal.
The input signal latching operation shown in the timing diagram of FIG. 19B will now be described.
The input signal goes “H” at time T01b, but the input signal being “H” is not latched because time T01b is after the rising edge of the clock. The input signal latching circuit 602 has latched, at the rising edge of the clock immediately before time T01b, the input signal being “L” before it goes “H”, whereby the latched signal is “L”.
Then, at time T02b, the input signal goes “L”, but the input signal being “L” is not latched because time T02b is after the rising edge of the clock. The input signal latching circuit 602 has latched, at the rising edge of the clock immediately before time T02b, the input signal being “H” before it goes “L”, whereby the latched signal is “H”.
Then, at time T03b, the input signal goes “H”, but the input signal being “H” is not latched because time T03b is after the rising edge of the clock. The input signal latching circuit 602 has latched, at the rising edge of the clock immediately before time T03b, the input signal being “L” before it goes “H”, whereby the latched signal is “L”.
Then, at time T04b, the input signal goes “L”, but the input signal being “L” is not latched because time T04b is after the rising edge of the clock. The input signal latching circuit 602 has latched, at the rising edge of the clock immediately before time T04b, the input signal being “H” before it goes “L”, whereby the latched signal is “H”.
With the timing shown in FIG. 19B, the input signal is output as the latched signal while being delayed by one clock cycle.
The input signal latching operation shown in the timing diagram of FIG. 19C will now be described.
As the input signal goes “H” at time T01c, the input signal being “H” is latched by the input signal latching circuit 602 at the following rising edge of the clock, thus bringing the latched signal to “H”.
As the input signal goes “L” at time T02c, the input signal being “L” is latched by the input signal latching circuit 602 at the following rising edge of the clock, thus bringing the latched signal to “L”.
Then, as the amount of delay of the input signal increases and the input signal goes “H” as late as at time T03c, the input signal being “H” is not latched because time T03c is after the rising edge of the clock. The input signal latching circuit 602 has latched, at the rising edge of the clock immediately before T03c, the input signal being “L” before it goes “H”, whereby the latched signal is “L”.
As the input signal goes “L” at time T04c, the input signal being “L” is latched by the input signal latching circuit 602 at the following rising edge of the clock, thus bringing the latched signal to “L”.
With the timing shown in FIG. 19C, the waveform of the input signal and that of the latched signal will be different from each other, and a signal different from the input signal will be given to the memory core 603.
In a memory system in which signals are exchanged in synchronism with a clock, the voltage conditions, the temperature conditions or the wire delay along the wires connecting the signal transmitting device with the signal receiving device may vary during operation, thus shifting the timing with which the signal receiving device receives the clock and the signal, thereby failing to satisfy the setup/hold time of the clock and the signal. This may cause an erroneous write, or an erroneous determination of the input signal by the signal receiving device. Particularly, where the clock frequency is high, it is difficult to set a setup/hold time such that the input signal is prevented from being determined erroneously by the signal receiving device, while taking the input timing into consideration.
There are techniques known in the art for the synchronous signal transfer operation, in which there is provided a circuit for delaying the clock and for determining a clock delay time such that the input signal is prevented from being determined erroneously (see, for example, Japanese Laid-Open Patent Publication No. 8-102729).
There are also other techniques known in the art for the synchronous signal transfer operation, in which there are provided a circuit for delaying the clock and the signal and a timer circuit for automatic timing adjustment, wherein a test for detecting a clock delay time such that the signal is prevented from being determined erroneously is performed for every passage of a period of time determined by the timer circuit (see, for example, Japanese Laid-Open Patent Publication No. 2001-154907).
With the technique of Japanese Laid-Open Patent Publication No. 8-102729, however, there is needed a clock test with human intervention in order to determine delay conditions. There is no countermeasures to a case where the clock and signal input timing varies due to variations in the voltage/temperature conditions during operation, or the like, and the predetermined delay setting is therefore no longer satisfied. Thus, the level of stability in practical operation is not sufficient.
With the technique of Japanese Laid-Open Patent Publication No. 2001-154907, the clock test for determining delay conditions requires registers for storing predetermined expected values. There are also needed a sequencer for realizing the clock test, and a timer circuit for executing the clock test at regular intervals. Since the clock test is not executed until the predetermined interval is over as measured by the timer circuit, signals may not be received normally if the clock and signal timing varies due to variations in the voltage/temperature conditions, or the like, before the next clock test is started.